With the introduction of low-voltage logic in the electronic circuit design, the inconsistent voltage between the input and output logic signals with the domains adds the complexity of system design. For example, when a digital circuit with 1.8V power supply is configured to communicate with an analog circuit with 3.3V power supply, level-shifter circuits are commonly used to change the voltage of the signals to be consistent. Level-shifter circuits are also essential between digital circuits with different logic signal voltage levels (e.g. TTL and CMOS). Level-shifter circuits are also used in low-power devices, such as internet of things (IOT) device, wearable device, and the like. Because low-power devices are sensitive to circuit power consumption, the power requirements for level-shifter circuits are also critical.
FIG. 1 shows a conventional level-shifter circuit 100. The level-shifter circuit 100 includes a first inverter (not labelled, see PMOS transistor P1 and NMOS transistor N1), a NMOS transistor N2, a second inverter (not labelled, see PMOS transistor P4 and NMOS transistor N3), a NMOS transistor N5, and a cross-coupled PMOS transistor P2 and a PMOS transistor P3. An input terminal of the first inverter receives a first digital signal (In). The first inverter and the second inverter are powered by a power supply voltage (e.g., 1.2 V) in a first power supply domain. The level-shifter circuit 100 shifts the voltage level of the first digital signal (In) to an appropriate range in a second power supply domain (for example, a supply voltage of 2.5 V), and then outputs a second digital signal (Out). The second digital signal (Out) is outputted through the drain of the PMOS transistor P2.
When the power supply voltage of the first power supply domain is powered off, the power supply voltage of the first inverter and the second inverter is switched off. Thus, the output terminals of the first inverter and the second inverter are at a floating status with respect to a ground reference. That is, the logic levels of their outputs are uncertain. In such situation, the NMOS transistor N2 and the NMOS transistor N5, which are cascaded with the first inverter and the second inverter, may be simultaneously turned on. The PMOS transistor P2 and the PMOS transistor P3 may be also simultaneously on because the voltage level of their gate terminals is equal to the ground reference voltage. Therefore, a leakage current in the second power domain can be generated through the PMOS transistor P2 and the NMOS transistor N2, or through the PMOS transistor P3 and the NMOS transistor N5, to the ground.
The above-described leakage current causes additional power consumption in the level-shifter circuit 100, which is unacceptable especially for a low-power consumption device.
The disclosed circuits are directed to at least partially alleviate one or more problems set forth above and to solve other problems in the art.